The present invention relates generally to a solid state image sensor system and a method for driving the same. More specifically, the invention relates to a solid state image sensor system having a plurality of pixel rows and a method for driving the same.
FIG. 4 shows the construction of a solid state image sensor system having a single pixel row, and FIG. 5 shows a time chart for transfer clocks "PHgr"1 and "PHgr"2, a reset pulse RS, a clock "PHgr"1B in the final stage of a shift register, and an output signal OS, which are used for reading signal charges of all of picture elements (pixels) in the system of FIG. 4.
In a pixel row 1 having a plurality of pixels xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c3xe2x80x9d, . . . , incident light is photoelectric-transferred to generate and store signal charges. The signal charges are transferred to an analog shift register 3 via a shift gate 2, which is arranged adjacent to the pixel row 1, as shown by arrows.
In the analog shift register 3, inverse-phase transfer clocks "PHgr"1 and "PHgr"2 are alternately applied to a transfer electrode (not shown). Thus, the signal charges are sequentially shifted to the left in the figure.
The signal charges transferred to the final stage 4 of the analog shift register 3 are sequentially given to a charge detecting part 5 in synchronism with a transfer clock "PHgr"1B. The charge detecting part 5 has a capacity 6 between a node ND, which is connected to the final stage 4, and a grounding terminal to detect a voltage corresponding to the quantity of signal charges stored in the capacity 6. This voltage is given to an output circuit 9 for amplifying the given voltage to a required level to output an output signal OS.
In addition, a reset gate transistor 7 is provided between the node ND and a reset drain 8, to which a power supply voltage is applied. When a reset pulse RS is applied to the gate of the reset gate transistor 7, the signal charges having been stored in the capacity 6 are discharged to the reset drain 8.
The output signal OS varies as shown in FIG. 5. If the reset pulse RS is given while the transfer clock "PHgr"1B in the final stage 4 is in a high level, a reset noise RN is generated in the output signal OS. After the reset noise RN is generated, the level of the output signal OS becomes a reference level RL. This reference level RL corresponds to an output level when no signal charge is stored in the capacity 6. Then, when the level of the transfer clock "PHgr"1B becomes a low level, the signal charges are transferred from the final stage 4 to the capacity 6 to be stored therein. At this time, the difference between the reference level RL and an output level OL1 corresponds to the quantity of the stored signal charges. Thus, the signal charges can be read out of all of pixels of the pixel row 1.
Then, when signal charges are read out of alternate pixels of the pixels 1, 2, 3, . . . , the system is driven in timing as shown in FIG. 6. Such a technique for reading signal charges out of alternate pixels to reduce resolution is used for reducing the quantity of data, for example.
Transfer clocks "PHgr"1 and "PHgr"2 applied to the transfer electrode of the analog shift register 3, and a transfer clock "PHgr"1B applied to the transfer electrode of the final stage 4 are the same as those when the signal charges are read out of all of the pixels as shown in FIG. 5. It is different from FIG. 5 that reset pulses RS given to the reset gate 7 are alternately generated.
In this case, the output signal OS outputted from the output circuit 9 is as follows. While the transfer clock "PHgr"1B is in a high level, after a reset noise RN is generated, the level of the output signal OS becomes the reference level RL. When the level of the transfer clock "PHgr"1B becomes a low level, the signal charges read out of the pixel 1 are stored in the capacity 6, and the level of the output signal OS becomes a level OL1 corresponding to the quantity of the stored signal charges. This level OL1 is held until the level of the next transfer clock "PHgr"1B falls to the low level after it becomes the high level. When it falls to the low level, the signal charges read out of the pixel 2 are added to the capacity 6. Thus, the level of the output signal OS becomes a level OL1+OL2 corresponding to the total quantity of the signal charges of the pixels 1 and 2.
In this case, the number of pixels, from which signal charges are read out, is reduced to half, so that the resolution is reduced to half.
When signal charges are read out of one pixel every n (n is an integer which is 2 or more) pixels, every time the level of the transfer clock "PHgr"1B falls from a high level to a low level, the level of the output signal OS varies so as to be sequentially OL1, OL1+OL2, . . . , OL1+ . . . +OLn. In this case, the resolution is reduced to 1/n.
FIG. 2 shows the construction of a solid state image sensor system wherein two pixel rows 1a and 1b are shifted by a width corresponding to xc2xd pixel to be arranged in a staggered form.
In the pixels xe2x80x9c1xe2x80x9d, xe2x80x9c3xe2x80x9d, xe2x80x9c5xe2x80x9d, of the pixel row 1a, incident light is photoelectric-transferred, so that signal charges are generated and stored. Similarly, in the pixels xe2x80x9c2xe2x80x9d, xe2x80x9c4xe2x80x9d, xe2x80x9c6xe2x80x9d, . . . of the pixel row 1b, incident light is photoelectric-transferred to generate and store signal charges. The signal charges are transferred from the pixel rows 1a and 1b to analog shift registers 3a and 3b via shift gates 2a and 2b, which are arranged adjacent to the pixel rows 1a and 1b, respectively.
In the analog shift registers 3a and 3b, inverse-phase transfer clocks "PHgr"1 and "PHgr"2 are alternately applied to transfer electrodes (not shown). Thus, the signal charges are sequentially shifted to the left in the figure.
The signal charges transferred to the final stages 4a and 4b of the analog shift registers 3a and 3b are sequentially given to a common charge detecting part 5 in accordance with transfer clocks "PHgr"1B and "PHgr"2B, respectively. The charge detecting part 5 has a capacity 6 between a node ND, which is connected to the final stages 4a and 4b, and a grounding terminal to detect a voltage corresponding to the quantity of signal charges stored in the capacity 6. This voltage is given to an output circuit 9 for amplifying the given voltage to a required level to output an output signal OS.
Similar to the system shown in FIG. 4, a reset gate transistor RS is provided between the node ND and a reset drain 8, to which a power supply voltage is applied. When a reset pulse RS is applied to the gate of the reset gate transistor RS, the signal charges having been stored in the capacity 6 are discharged to the reset drain 8.
In this case, the output signal OS varies as shown in FIG. 7. If the reset pulse RS is given while the transfer clock "PHgr"1B in the final stage 4a, to which the signal charges are transferred from the pixel row 1a, is in a high level, a reset noise RN is generated in the output signal OS. After the reset noise RN is generated, the level of the output signal OS becomes a reference level RL. When the level of the transfer clock "PHgr"1B becomes a low level, the signal charges are transferred from the final stage 4a to the capacity 6 to be stored therein. At this time, the difference between the reference level RL and an output level OL1 corresponds to the quantity of the stored signal charges generated from the pixel xe2x80x9c1xe2x80x9d.
Then, if the reset pulse RS is given while the transfer clock "PHgr"2B in the final stage 4b, to which the signal charges are transferred from the pixel row 1b, is in a high level, a reset noise RN is generated in the output signal OS. After the reset noise RN is generated, the level of the output signal OS becomes the reference level RL. When the level of the transfer clock "PHgr"2B becomes a low level, the signal charges are transferred from the final stage 4b to the capacity 6 to be stored therein. At this time, the difference between the reference level RL and an output level OL2 corresponds to the quantity of the stored signal charges generated from the pixel xe2x80x9c2xe2x80x9d. Thus, the signal charges can be alternately read out of all of the pixels xe2x80x9c1xe2x80x9d, xe2x80x9c2xe2x80x9d, xe2x80x9c3xe2x80x9d, xe2x80x9c4xe2x80x9d, . . . of the pixel rows 1a and 1b. 
Then, a case where signal charges are read out of alternate pixels of the system shown in FIG. 2 will be described. In this case, a driving waveform is shown in FIG. 8. Transfer clocks "PHgr"1 and "PHgr"2, which are applied to the transfer electrodes of the analog shift register 3a and 3b, respectively, and transfer clocks "PHgr"1B and "PHgr"2B , which are applied to the transfer electrodes of the final stages 4a and 4b, respectively, are the same as those when the signal charges are read out of all of the pixels as shown in FIG. 5. It is different from FIG. 5 that reset pulses RS given to the reset gate 7 are generated in alternate cycles.
In this case, the output signal OS outputted from the output circuit 9 is as follows. While the transfer clock "PHgr"2B in the final stage 4b is in a high level, after a reset noise RN is generated, the level of the output signal OS becomes the reference level RL. When the level of the transfer clock "PHgr"2B becomes a low level, the signal charges read out of the pixel 2 are stored in the capacity 6, and the level of the output signal OS becomes a level OL2 corresponding to the quantity of the stored signal charges.
While the transfer clock "PHgr"2B is in the low level, the transfer clock "PHgr"1B in the final stage 4a is in the high level. When the transfer clock "PHgr"1B falls to the low level, the signal charges read out of the pixel 3 are stored in the capacity 6. Thus, the output level OS becomes an output level OL2+OL3 obtained by adding the signal charges of the pixel 3 to the signal charges of the pixel 2, which have been already stored. This output level OL2+OL3 is held until the next reset pulse is outputted.
In this case, the number of pixels, from which signal charges are read out, is reduced to half, so that the resolution is reduced to half. If n pixel rows are provided and if signal charges read out of n pixels of each of the pixel rows are outputted together as one output level, every time the levels of the transfer clocks "PHgr"1B, "PHgr"2B, . . . , "PHgr"nB fall to a low level, the level of the output signal OS varies so as to be sequentially OL1, OL1+OL2, . . . , OL1+ . . . +OLn. In this case, the resolution is reduced to 1/n.
However, in the solid state image sensor system shown in FIG. 2 wherein the plurality of pixel rows are arranged, the pixel row 1a is spaced from the pixel row 1b by a distance D. Therefore, if the signal charges from the pixel xe2x80x9c3xe2x80x9d, of the pixel row 1a are added to the signal charges from the pixel xe2x80x9c2xe2x80x9d of the pixel row 1b to output the output level OL2+OL3, there is a problem in that the obtained image deteriorates.
It is therefore an object of the present invention to eliminate the aforementioned problems and to provide a solid state image sensor system which is provided with a plurality of pixel rows and which is capable of preventing the deterioration of an image even if the number of output signals is reduced to 1/n of the number of pixels to read out signal charges at a resolution of 1/n.
In order to accomplish the aforementioned and other objects, according to one aspect of the present invention, a solid state image sensor system comprises n (n is an integer which is 2 or more) pixel rows, each of which has pixels arranged in a row, each of the pixels being irradiated with light to carry out a photoelectric transfer to generate a signal charge, wherein only a signal charge, which is generated in one of the n pixel rows, is read out when the signal charge is read out at a resolution of 1/n.
According to another aspect of the present invention, a solid state image sensor system comprises n (n is an integer which is 2 or more) pixel rows, each of which has pixels arranged in a row, each of the pixels being irradiated with light to carry out a photoelectric transfer to generate a signal charge, wherein signal charges, which are generated from adjacent m pixels of one of the n pixel rows, are added up to read out signal charges, which are generated in the one of the n pixel rows, when the signal charges are read out at a resolution of 1/n*m (m is an integer which is 2 or more).
According to another aspect of the present invention, a solid state image sensor system comprises: n (n is an integer which is 2 or more) pixel rows, each of which has pixels arranged in a row, each of the pixels being irradiated with light to carry out a photoelectric transfer to generate a signal charge; n analog shift registers, each of which is provided for each of the pixel rows to sequentially transfer a signal charge, which is generated from a corresponding one of the pixel rows; a charge detecting part, which is provided commonly for all of the analog shift registers, and to which signal charges are alternately given from a final stage of each of the analog shift registers, for storing and detecting the signal charges; and a reset drain for discharging the signal charges stored in the charge detecting part, wherein when the signal charges are read out at a resolution of 1/n, signal charges generated in one of the n pixel rows are detected by the charge detecting part, and signal charges generated in other nxe2x88x921 pixel rows of the n pixel rows are discharged to the reset drain.
According to a further aspect of the present invention, there is provided a method for driving a solid state image sensor system comprising n (n is an integer which is 2 or more) pixel rows, each of which has pixels arranged in a row, each of the pixels being irradiated with light to carry out a photoelectric transfer to generate a signal charge, wherein the solid state image sensor system is driven so as to read out only a signal charge, which is generated in one of the n pixel rows, when the signal charge is read out at a resolution of 1/n.
According to a still further aspect of the present invention, there is provided a method for driving a solid state image sensor system comprising n (n is an integer which is 2 or more) pixel rows, each of which has pixels arranged in a row, each of the pixels being irradiated with light to carry out a photoelectric transfer to generate a signal charge, wherein the solid state image sensor system is driven so as to add up signal charges, which are generated from adjacent m pixels of one of the n pixel rows, to read out signal charges, which are generated in the one of the n pixel rows, when the signal charges are read out at a resolution of 1/n*m (m is an integer which is 2 or more).
According to the above described solid state image sensor system and method for driving the same, even if a reading resolution is reduced to 1/n in the system having n pixel rows, it is possible to obtain a desired resolution without deteriorating images by reading signal charges out of only one of the pixel rows and discarding all of signal charges from other pixel rows. In addition, it is possible to obtain a resolution of 1/m*n while preventing the deterioration of images by adding up and reading signal charges of adjacent m pixels in one of the n pixel rows.